Field of the Disclosure
The present disclosure relates to three-dimensional (3D) memory devices, and more particularly to methods to fabricate such memory devices.
Description of Related Art
Three dimensional (3D) semiconductor devices are characterized by multiple layers forming a stack of alternating active layers and insulating layers. In a memory device, each of the layers can include a planar array of memory cells. For certain three-dimensionally stacked memory devices, active layers can comprise active strips of materials configured as bit lines or word lines for memory cells stacked in spaced-apart ridge-like structures. The active layers can be made from a conductor, an undoped semiconductor, or a doped (p-type or n-type) semiconductor. In such 3D memory, memory cells can be disposed at the cross-points of the stacked bit lines or word lines and the crossing word lines or bit lines, forming a 3D memory array.
Active layers can be formed of semiconductor material and then etched to form active strips. The pattern of doping in the active strips can be a critical factor affecting the performance of memory cells including the active strips. For example, the current through a NAND string in a 3D NAND structure is limited by the doping in portions of the active strips between string select structures (SSLs) and bit line pad regions, and between memory cells and a ground select line (GSL).
It is desirable to provide a method for improving control of doping concentration in the active strips, including in portions of the active strips between SSLs and bit line pad regions, between SSLs and GSL, and in other parts of the active strips.